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d a t a sh eet preliminary speci?cation supersedes data of july 1993 file under integrated circuits, ic01 1995 dec 18 integrated circuits TDA1311A stereo continuous calibration dac (cc-dac)
1995 dec 18 2 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A features voltage output space saving packages so8 or dip8 low power consumption wide dynamic range (16-bit resolution) continuous calibration (cc) concept easy application: C single 4 to 5.5 v rail supply C output current and bias current are proportional to the supply voltage C integrated current-to-voltage converter fast settling time permits 2, 4 and 8 oversampling (serial input) or double-speed operation at 4 oversampling internal bias current ensures maximum dynamic range wide operating temperature range ( - 40 c to +85 c) compatible with most current japanese input formats: time multiplexed, two's complement, ttl no zero-crossing distortion cost efficient. general description the TDA1311A; at is a voltage-driven digital-to-analog converter and is new generation of dac devices which embodies the innovative technique of continuous calibration (cc). the largest bit-currents are repeatedly generated by one single current reference source. this duplication is based upon an internal charge storage principle which has an accuracy insensitive to ageing, temperature matching and process variations. the TDA1311A; at is fabricated in a 1.0 m m cmos process and features an extremely low-power dissipation, small package size and easy application. furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. therefore, the cc-dac is eminently suitable for use in (portable) digital audio equipment. ordering information type number package name description version TDA1311A dip8 plastic dual in-line package; 8 leads (300 mil) sot97-1 TDA1311At so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1
1995 dec 18 3 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage 4 5 5.5 v i dd supply current v dd = 5 v at code 0000h - 3.4 6.0 ma v fs full scale output voltage v dd = 5 v 1.8 2.0 2.2 v (thd+n)/s total harmonic distortion plus noise at 0 db signal level -- 68 - 63 db - 0.04 0.07 % at - 60 db signal level -- 30 - 24 db - 36% at - 60 db signal level; a-weighted -- 33 - db - 2 - % s/n signal-to-noise ratio at bipolar zero a-weighted at code 0000h 86 92 - db t cs current settling time to 1 lsb - 0.2 -m s br input bit rate at data input -- 18.4 mbits/s f bck clock frequency at clock input -- 18.4 mhz tc fs full scale temperature coef?cient at analog outputs (i ol ; i or ) - 400 - ppm t amb operating ambient temperature - 40 - +85 c p tot total power dissipation v dd = 5 v at code 0000h - 17 30 mw
1995 dec 18 4 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A block diagram fig.1 block diagram. handbook, full pagewidth mbg858 32 (5-bit) calibrated current sources 1 calibrated spare source 11-bit passive divider left bit switches 6 i/v left input register left output register right bit switches right input register right output register 8 i/v 32 (5-bit) calibrated current sources 1 calibrated spare source 11-bit passive divider reference source control and timing 1 2 3 5 4 c2 100 nf v dd v or i or gnd TDA1311A TDA1311At v ol bck ws data i ol pinning symbol pin description bck 1 bit clock input ws 2 word select input data 3 data input gnd 4 ground v dd 5 supply voltage v ol 6 left channel output n.c. 7 not connected v or 8 right channel output fig.2 pin configuration. handbook, halfpage 1 2 3 4 8 7 6 5 mbg859 TDA1311A TDA1311At bck ws data gnd v dd v ol v or n.c.
1995 dec 18 5 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A functional description the basic operation of the continuous calibration dac is illustrated in fig.3. the figure shows the calibration and operation cycle. during calibration of the mos current source (see fig.3a) transistor m1 is connected as a diode by applying a reference current. the voltage v gs on the intrinsic gate-source capacitance c gs of m1 is then determined by the transistor characteristics. after calibration of the drain current to the reference value i ref , the switch s1 is opened and s2 is switched to the other position (see fig.3b). the gate-to-source voltage v gs of m1 is not changed because the charge on c gs is preserved. therefore, the drain current of m1 will still be equal to i ref and this exact duplicate of i ref is now available at the out terminal. the 32 current sources and the spare current source of the TDA1311A; at are continuously calibrated (see fig.1). the spare current source is included to allow continuous converter operation. the output of one calibrated source is connected to an 11-bit binary current divider consisting of 2048 transistors. a symmetrical offset decoding principle is incorporated that arranges the bit switching in such a way that the zero-crossing is performed only by switching the lsb currents. the TDA1311A; at (cc-dac) accepts serial input data formats of 16-bit word length. left and right data words are time multiplexed. the most significant bit (bit 1) must always be first. the input data format is shown in figs 4 and 5. with a high level on the word select input (ws), data is placed in the left input register and with a low level on the ws input, data is placed in the right input register (see fig.1). the data in the input registers are simultaneously latched in the output registers which control the bit switches. an internal offset voltage v os is added to the full scale output voltage v fs ; v os and v fs are proportional to v dd : v dd1 /v dd2 =v fs1 /v fs2 =v os1 /v os2 . fig.3 calibration principle. handbook, full pagewidth mbg860 out s2 s1 m1 c gs v gs c gs v gs out s2 s1 m1 i ref i ref i ref (a) (b) (a) = calibration. (b) = operation.
1995 dec 18 6 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A limiting values in accordance with the absolute maximum rating system (iec 134). note 1. human body model: c = 100 pf, r = 1500 w , 3 pulses positive and 3 pulses negative. 2. machine model: c = 200 pf, l = 0.5 m h, r = 10 w , 3 pulses positive and 3 pulses negative. thermal resistance quality specification in accordance with snw-fq-0611. characteristics v dd =5v; t amb =25 c; measured in fig.1; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage - 6.0 v t stg storage temperature - 55 +150 c t xtal maximum crystal temperature - +150 c t amb operating ambient temperature - 40 +85 c v es electrostatic handling note 1 - 2000 +2000 v note 2 - 200 +200 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air dil8 100 k/w so8 210 k/w symbol parameter conditions min. typ. max. unit supply v dd supply voltage 4.0 5.0 5.5 v i dd supply current at code 0000h - 3.4 6.0 ma digital inputs; pins ws, bck and data | i il | input leakage current low v i = 0.8 v -- 10 m a | i ih | input leakage current high v i = 2.4 v -- 10 m a f bck clock frequency -- 18.4 mhz br bit rate data input -- 18.4 mbits/s f ws word select input frequency -- 384 khz
1995 dec 18 7 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A note 1. measured with 1 khz sinewave generated at sampling rate of 192 khz. timing (see fig.4) t r rise time -- 12 ns t f fall time -- 12 ns t cy bit clock cycle time 54 -- ns t bckh bit clock pulse width high 15 -- ns t bckl bit clock pulse width low 15 -- ns t su;dat data set-up time 12 -- ns t hd:dat data hold time to bit clock 2 -- ns t hd:ws word select hold time 2 -- ns t su;ws word select set-up time 12 -- ns analog outputs; pins v ol and v or v fs full-scale voltage 1.8 2.0 2.2 v tc fs full-scale temperature coef?cient - 400 - ppm v os offset voltage v dd =v ol/ormax 0.45 0.50 0.55 v (thd+n)/s total harmonic distortion plus noise at 0 db signal level; note 1 -- 68 - 63 db - 0.04 0.07 % at - 60 db signal level; note 1 -- 30 - 24 db - 36 % at - 60 db signal level; a-weighted; note 1 -- 33 - db - 2 - % at 0 db signal level; f = 20 hz to 20 khz -- 65 - 61 db - 0.05 0.09 % t cs current settling time to 1 lsb - 0.2 -m s a cs channel separation 75 80 - db |d i o | unbalance between outputs note 1 - 0.2 0.3 db | t d | time delay between outputs - 0.2 -m s s/n signal-to-noise ratio at bipolar zero a-weighted at code 0000h 86 92 - db symbol parameter conditions min. typ. max. unit
1995 dec 18 8 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A fig.4 timing and input signals. handbook, full pagewidth mbg861 sample out ws bck data right lsb msb left t hd; ws t su; ws t su; dat t hd; dat t bckl t bckh t f t r > 12 > 15 > 15 t cy > 54 < 12 < 12 > 2 > 12 > 2
1995 dec 18 9 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A handbook, full pagewidth mbg862 lsb msb lsb msb data bck ws left right sample out fig.5 format of input signals.
1995 dec 18 10 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A application information basic application example a typical example of a cd-application with the TDA1311A; at is shown in fig.6. it features typical decoupling components and a third-order analog post-filter stage providing a line output. fig.6 example of a 3rd order filter application. handbook, full pagewidth 100 pf 22 k w 420 pf 22 k w 2.2 nf TDA1311A TDA1311At 5 8 7 6 4 1 2 3 bck ws data 100 pf 22 k w 420 pf 22 k w 2.2 nf 100 nf 47 m f v dd 10 w mbg863 attention to printed circuit board layout the TDA1311A and even more so the TDA1311At offers great ease in designing-in to printed-circuit boards due to its small size and low pin count. the TDA1311A; at being a mixed-signal ic in cmos, some attention needs to be paid to layout and topology of the application pcb. following some basic rules will yield the desired performance. the most important considerations are: 1. supply: care should be taken to supply the TDA1311A; at with a clean, noiseless v dd , for a good noise performance of the analog parts of the dac. supply purity can easily be achieved by using an rc-filtered supply. 2. grounding: preferably a ground plane should be used, in order to have a low-impedance return available at any point in the layout. it is advantageous to make a partitioning of the ground plane according to the nature of the expected return currents (digital input returns separate from supply returns and separate from the analog section). 3. topology: the capacitor decoupling high-frequency supply interference from v dd to gnd should be placed as close as is physically possible to the ic body, ensuring a low-inductance path to ground. the digital input conductors may be shielded by ground leads running alongside. the placement of a passive ground plane underside the entire ic surface gives `free` additional decoupling from the ic body to ground as well as providing a shield between the digital input pins and the analog output pins. figure 7 shows recommended layouts for printed-circuit boards for the so8 and dil8 versions respectively. both layouts use a single-interconnect layer.
1995 dec 18 11 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A fig.7 recommended printed-circuit board layouts. handbook, full pagewidth msa739 v dd r v dd c1 c2 interface examples the following figures (figs 8 to 14) show examples of connections to commonly used decoder and digital filter ics. the digital interface part is shown only, for clarity. the diagrams are for guidance purposes only - no guarantee for industrial exploitation is implied. fig.8 npc sm5807 digital filter (4fs). handbook, halfpage sm5807 15 bcko 14 lrcon 12 dout TDA1311A TDA1311At 1 bck 2 ws 3 data 1 remark: scsln - signal sm5807 both "l" and "h" supported by TDA1311A and TDA1311At mbg864
1995 dec 18 12 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A fig.9 npc sm5840 digital filter (4fs). handbook, halfpage sm5840 (1) 14 dol 13 dor 12 bcko TDA1311A TDA1311At 1 bck 2 ws 3 data omodn pin 19: "l" for 4fs operation (1) versions a/b/g mbg865 fig.10 sony cxd1125 decoder (1fs). handbook, halfpage cxd1125 76 c2ion 80 lrck 78 data TDA1311A TDA1311At 1 bck 2 ws 3 data mode select: md1 pin 55: "l" md2 pin 56: "l" to use dotx function md3 pin 57: "h" pssl pin 59: "l" slob pin 58: "l" mbg866 fig.11 sony cxd1162 digital filter (4fs). handbook, halfpage cxd1125 3 c2ion 1 lrd 4 data TDA1311A TDA1311At 1 bck 2 ws 3 9 7 8 data bck lrck data remark: cxd1162 input connectable to cxd1125 in the same way as for TDA1311A; at to cxd1125 mbg867
1995 dec 18 13 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A fig.12 sony cxd1135 decoder (1fs) and digital filter (2fs). handbook, halfpage cxd1135 76 da14 80 lrck 78 da16 TDA1311A TDA1311At 1 bck 2 ws 3 data mode select: md1 pin 55: "l" md2 pin 56: "l" to use dotx function md3 pin 57: "h" for 1fs; "l" for 2fs pssl pin 59: "l" slob pin 58: "l" mbg868 fig.13 mitsubishi m50423 decoder (1fs) and digital filter (4fs). handbook, halfpage m50423 74 dsck 75 lrck 72 do1 TDA1311A TDA1311At 1 bck 2 ws 3 data mode select: dobsel pin 7: "l" dasel1 pin 8: "h" dasel2 pin 9: "l" dasel3 pin 10: "h" dasel4 pin 11: "l" mbg869 fig.14 sanyo lc7863 decoder (1fs). handbook, halfpage lc7863 35 daclk 30 lrclk 34 dfout TDA1311A TDA1311At 1 bck 2 ws 3 data mode select: dfoff pin 27: "l" msbf pin 38: "h" mbg870
1995 dec 18 14 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A evaluation of audio parameters the following measurement graphs are performed on singular engineering samples; therefore no guarantee of typical parameter values is implied. measurement conditions are typical, as stated in the section characteristics, unless otherwise indicated. the normal measurement set-up includes a 20 khz band-limiting filter for bandwidth definition, and an a-weighting filter where indicated. fig.15 total harmonic distortion plus noise as a function of signal level (4fs). handbook, halfpage - 100 - 80 - 60 - 40 - 20 0 thd (db) signal level (db) - 100 - 80 - 60 - 40 - 20 0 mbg871 fig.16 total harmonic distortion plus noises as a function of frequency (4fs). (1) measured including all distortion plus noise at a signal level of - 60 db. (2) measured including all distortion plus noise at a signal level of 0 db. handbook, halfpage mbg873 10 2 10 3 10 4 10 5 10 frequency (hz) thd (db) thd (%) - 20 10 1 0.1 0.01 0.001 - 40 - 60 - 80 - 100 (1) (2)
1995 dec 18 15 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A fig.17 total harmonic distortion plus noise as a function of supply voltage (4fs). (1) measured including all distortion plus noise within the specified operating supply voltage range. (2) measured including all distortion plus noise outside the specified operating supply voltage range. (3) v fs relative to nominal. handbook, halfpage 3 thd (db) thd (%) 46 v dd (v) - 50 - 60 - 70 - 80 20 0 - 20 - 40 mbg872 5 (1) (3) (2)
1995 dec 18 16 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A package outlines references outline version european projection issue date iec jedec eiaj sot97-1 92-11-17 95-02-04 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.14 0.53 0.38 0.36 0.23 9.8 9.2 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 1.15 4.2 0.51 3.2 inches 0.068 0.045 0.021 0.015 0.014 0.009 1.07 0.89 0.042 0.035 0.39 0.36 0.26 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.045 0.17 0.020 0.13 b 2 050g01 mo-001an m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 8 1 5 4 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. pin 1 index dip8: plastic dual in-line package; 8 leads (300 mil) sot97-1
1995 dec 18 17 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03s ms-012aa 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.050 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 95-02-04 97-05-22
1995 dec 18 18 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1995 dec 18 19 philips semiconductors preliminary speci?cation stereo continuous calibration dac (cc-dac) TDA1311A definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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(02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-2724825 scd47 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 513061/50/02/pp20 date of release: 1995 dec 18 document order number: 9397 750 00532

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